1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device possessing a lightly doped drain (LDD) region. More particularly, the invention relates to a method of manufacturing a thin film transistor (TFT) possessing a gate electrode which is covered by an oxide film.
The invention further relates to a method of forming an insulated gate type semiconductor device which is formed on an insulating surface and possesses a silicon active layer in the form of a thin film and of forming an integrated circuit in which a large number of these devices are formed. The semi-conductor devices of the invention can be used as thin film transistors or integrated circuits of such transistors in the drive circuits of active matrices such as liquid crystal displays, etc. or image sensors, etc. or in SOI integrated circuits and conventional integrated circuits (microprocessors, microcontrollers, microcomputers and semiconductor memories, etc.). In the invention, ‘insulating surface’ does not just mean the surface of an insulating substrate but also includes the surface of insulating films that are provided on semiconductors or conductors.
2. Description of the Related Art
In recent years, the formation of insulated gate semiconductor devices (or MOSFETs) on insulating surfaces has been tried. Such formation of semiconductor integrated circuits on insulating surfaces is advantageous in respect of high-speed drive of circuits, since, as opposed to conventional semiconductor integrated circuits in which the speed is mainly governed by the capacitance (stray capacitance) of the wiring and the substrate, this stray capacitance is not present on an insulating substrate. A MOSFET which is formed on an insulating substrate in this manner and possesses an active layer in the form of a thin film is called a thin film transistor (TFT). TFTs are essential for the purpose of raising the level of integration, and also for the purpose of forming integrated circuits as multilayer circuits. For example, TFTs are used as SRAM load transistors in semiconductor integrated circuits. It is also known to form TFTs for the purpose of driving active matrix type liquid crystal displays and image sensors, etc. In particular, because of the need for high-speed operation, crystalline silicon TFTs, with which mobility is higher, have recently been developed in place of amorphous silicon TFTs, in which amorphous silicon is used for the active layer.
If thin film transistors are to be used as drive elements in the individual pixel regions of an active matrix type liquid crystal display, it is necessary that the value of their off current be small. ‘Off current’ is the current that flows between the source and drain even though the thin film transistor is in the ‘off state’. If the value of this off current is large, the charge held for a pixel falls, and it becomes impossible to maintain a screen display for a set time. The reason why off current occurs is that the thin film transistor constituting the active layer possesses a poly-crystalline structure or a microcrystalline structure.
For example, when an N-channel thin film transistor is in the off state, a negative voltage is imposed on the gate electrode. In this condition, the region of the channel-forming region which contacts the gate insulation film is P-type. Therefore, a PN junction is formed between the source and drain, and so hardly any current should flow. When, however, the active layer is constituted by a silicon film possessing a polycrystalline or a microcrystalline structure, migration of carriers (charges) via the crystal grain boundaries occurs, and this is the cause of off current.
An LDD (lightly doped drain) structure and an offset gate structure are known as structures for making this off current small. These are structures which are designed, mainly, to reduce the electric field strength at and in the vicinity of the interface of the channel-forming region and the drain region and thereby suppress migration of carriers via the crystal grain boundaries in this region.
However, in the case of TFTs, unlike the case with known semiconductor integrated circuit technology, there are still many problems that need to be solved, and there is the problem that it is difficult to produce required LDD structures or offset gate structures. In particular, when it is attempted to form a TFT on an insulating substrate such as a glass substrate, etc., there is the problem that, since the substrate becomes electrostatically charged, reactive ion anisotropic etching fails to function properly and etching therefore becomes unstable, and there is, for example, the problem that it is difficult to form fine patterns with good control.
FIG. 7 shows cross-sections of a typical LDD manufacturing process that has been employed hitherto. First, a base film 702 is formed on a substrate 701, and an active layer is formed with crystalline silicon 703. Then, an insulation film 704 is formed with material such as silicon oxide, etc. on this active layer. (FIG. 7(A))
Next, a gate electrode 705 is formed with polycrystalline silicon (doped with an impurity such as phosphorus, etc.), or with tantalum, titanium or aluminum, etc. Using this gate electrode as a mask, an impurity element (phosphorus or boron) is introduced by ion doping or a similar means, thereby forming, in a self-aligning manner in the active layer 703, lightly doped drain (LDD) regions 706 and 707 in which the dopant dose is small. The active layer region which is below the gate electrode and into which an impurity has not been introduced comes to constitute a channel-forming region. The impurity with which doping has been effected is then activated by a heat source such as a laser or a flashlamp, etc. (FIG. 7(B))
Next, an insulation film 708 of silicon oxide, etc. is formed by plasma CVD, LPCVD or a similar means (FIG. 7(C)), and anisotropic etching of this film is effected to form a sidewall 709 adjacent the side surface of the gate electrode. (FIG. 7(D))
Then, the impurity element is introduced again, by ion doping or a similar means, and, since the gate electrode 705 and sidewall 709 are used as a mask, regions (source/drain regions) 710 and 711 with quite a high impurity concentration are formed in a self-aligning manner in the active layer 703. The doping impurity is then activated by a heat source such as a laser or a flashlamp, etc.
Finally, a layer insulator 712 is formed, contact holes are formed going through the layer insulator to the source/drain regions, and wiring/electrodes 713 and 714 that connect to the source and drain are formed with metal material such as aluminum, etc. (FIG. 7(F))
Recently, products that require semiconductor integrated circuits to be formed on transparent insulating substrates have made an appearance. Examples are the drive circuits of optical devices such as liquid crystal displays and image sensors. TFTs are also used in these circuits. These circuits are required to be formed with a large surface area, and a reduction in the temperature of the TFT manufactory process is therefore required. Also, in cases where a device with a large number of terminals is on an insulating substrate and these terminals have to be connected to a semiconductor integrated circuit, consideration has been given to forming the actual semiconductor integrated circuit itself or its first stage monolithically on the same insulating substrate in order to reduce the packaging density.
Conventionally, a TFT is produced by annealing an amorphous, semi-amorphous or microcrystalline silicon film at a temperature of 450-1200° C., to increase its crystallinity and improve it to a good-quality silicon film (ie, one with which mobility is sufficiently great), and using this as an active layer. There also exist amorphous silicon TFTs using amorphous silicon for the active layer, but the mobility in them is low, being 5 cm2/Vs, normally about 1 cm2/Vs, and considerations of operating speed, and also consideration of the fact that they do not permit production of P-channel TFTs mean that there are considerable restrictions on their use. Annealing at a temperature such as noted above is necessary in order to produce a TFT in which the mobility is 5 cm2/Vs. This annealing also makes it possible to produce a P-channel TFT (a PTFT).
Producing a high mobility TFT necessitates reducing the source/drain sheet resistance as well as that of the active layer. In particular, if the aim is to produce a TFT in which the field mobility exceeds 150 cm2/Vs, the sheet resistance must be 200 Ω/square, and, in view of this, a method using silicides for portions corresponding to the source/drain has been proposed.
FIG. 14 shows cross-sections of a typical currently devised TFT manufacturing process in which a silicide is used in order to reduce the sheet resistance of the portion corresponding to the source/drain section. First, a silicon active layer 1403 in the form of an island is formed on a substrate 1401. If required, a base film 1402 may be formed between the substrate and the active layer. Then, an insulation film 1404 that functions as a gate insulation film is formed with material such as silicon oxide, etc., on the active layer. (FIG. 14(A))
Next, a gate electrode 1405 is formed with poly-crystalline silicon (doped with an impurity such as phosphorus, etc. in order to lower the resistance), etc. Then, with this gate electrode as a mask, an impurity element (phosphorus or boron) is introduced by ion doping or a similar means, and impurity regions 1406 are formed in a self-aligning manner in the active layer 1403. The active layer region which is below the gate electrode and into which an impurity has not been introduced comes to constitute a channel-forming region. Then, the doping impurity is activated by thermal annealing, laser annealing, flashlamp annealing, rapid thermal annealing or a similar means. (FIG. 14(B))
Next, an insulation film 1407 of silicon oxide, etc. is formed by plasma CVD, LPCVD or a similar means (FIG. 14(C)), and a sidewall A1408 adjacent the side surface of the gate electrode is formed by anisotropic etching of this insulation film, by reactive ion etching or a similar means. (FIG. 14(D))
Then, a covering 1409 of a metal (eg, titanium, tungsten, molybdenum, platinum, or chromium, etc.) for forming a silicide over the whole surface is formed. (FIG. 14(E))
This is followed by thermal annealing, laser annealing or a similar means to react the metal covering 1409 and the impurity regions 1406 closely bonded thereto, and so form silicide regions 1410. At this time, the impurity region portions 1411 that are below the sidewall A1408 remain as impurity regions, since the metal covering 1409 is not formed on them. If silicon is used for the gate electrode, a silicide is also formed on the top surface of the gate electrode. On the other hand, the metal film deposited on the insulation film (silicon oxide, etc.) hardly reacts at all, and so a portion of the metal covering 1409 becomes a silicide, and the other portion thereof remains unreacted.
If, at this time, the ratio of the etching rates of the metal covering 1409 and its silicide is sufficiently great, it is possible to etch away only the unreacted metal covering. All the metals noted above are suitable for this purpose, since their etching rates are greater than those of their silicides. (FIG. 14(F))
Finally, a layer insulator 1412 is formed, contact holes going through the layer insulator to the source/drain regions are formed, and wiring/electrodes 1413 connecting to the source and drain are formed with metal material such as aluminum, etc. (FIG. 14(G))
In the element thus produced, the resistance of the silicide regions 1410 is much smaller than that of ordinary doped silicon doped with phosphorus or boron, and it can be effectively ignored. Therefore, what actually determines the source/drain sheet resistance is the width x of an impurity region 1411 below the sidewall, and since this is very small, it is possible to produce a TFT in which the source/drain sheet resistance is satisfactorily small.